Method and apparatus for video coding

ABSTRACT

In a method of video decoding at a video decoder, a first high level syntax (HLS) element and a second HLS element can be received. The first HLS element can indicate whether an explicit multiple transform selection (MTS) is enabled or disabled for an intra coded block. The second HLS element can indicate whether the explicit MTS is enabled or disabled for an inter coded block. The first and second HLS elements can control a same set of coding blocks that include the intra coded block and the inter coded block. An implicit MTS can be enabled for the intra coded block when the first HLS element indicates the explicit MTS is disabled for the intra coded block, and the second HLS element indicates the explicit MTS is enabled for the inter coded block.

INCORPORATION BY REFERENCE

This application is a continuation of U.S. application Ser. No.17/463,826, filed Sep. 1, 2021, which is continuation of U.S.application Ser. No. 16/878,390, filed May 19, 2020, which claims thebenefit of priority to U.S. Provisional Application No. 62/860,149,“High-level Syntax Control on Enabling Implicit Transform Selection”filed on Jun. 11, 2019. The disclosures of all the prior applicationsare incorporated by reference herein in their entirety.

TECHNICAL FIELD

The present disclosure describes embodiments generally related to videocoding.

BACKGROUND

The background description provided herein is for the purpose ofgenerally presenting the context of the disclosure. Work of thepresently named inventors, to the extent the work is described in thisbackground section, as well as aspects of the description that may nototherwise qualify as prior art at the time of filing, are neitherexpressly nor impliedly admitted as prior art against the presentdisclosure.

Video coding and decoding can be performed using inter-pictureprediction with motion compensation. Uncompressed digital video caninclude a series of pictures, each picture having a spatial dimensionof, for example, 1920×1080 luminance samples and associated chrominancesamples. The series of pictures can have a fixed or variable picturerate (informally also known as frame rate), of, for example 60 picturesper second or 60 Hz. Uncompressed video has significant bitraterequirements. For example, 1080p60 4:2:0 video at 8 bit per sample(1920×1080 luminance sample resolution at 60 Hz frame rate) requiresclose to 1.5 Gbit/s bandwidth. An hour of such video requires more than600 GBytes of storage space.

One purpose of video coding and decoding can be the reduction ofredundancy in the input video signal, through compression. Compressioncan help reduce the aforementioned bandwidth or storage spacerequirements, in some cases by two orders of magnitude or more. Bothlossless and lossy compression, as well as a combination thereof can beemployed. Lossless compression refers to techniques where an exact copyof the original signal can be reconstructed from the compressed originalsignal. When using lossy compression, the reconstructed signal may notbe identical to the original signal, but the distortion between originaland reconstructed signals is small enough to make the reconstructedsignal useful for the intended application. In the case of video, lossycompression is widely employed. The amount of distortion tolerateddepends on the application; for example, users of certain consumerstreaming applications may tolerate higher distortion than users oftelevision distribution applications. The compression ratio achievablecan reflect that: higher allowable/tolerable distortion can yield highercompression ratios.

A video encoder and decoder can utilize techniques from several broadcategories, including, for example, motion compensation, transform,quantization, and entropy coding.

Video codec technologies can include techniques known as intra coding.In intra coding, sample values are represented without reference tosamples or other data from previously reconstructed reference pictures.In some video codecs, the picture is spatially subdivided into blocks ofsamples. When all blocks of samples are coded in intra mode, thatpicture can be an intra picture. Intra pictures and their derivationssuch as independent decoder refresh pictures, can be used to reset thedecoder state and can, therefore, be used as the first picture in acoded video bitstream and a video session, or as a still image. Thesamples of an intra block can be exposed to a transform, and thetransform coefficients can be quantized before entropy coding. Intraprediction can be a technique that minimizes sample values in thepre-transform domain. In some cases, the smaller the DC value after atransform is, and the smaller the AC coefficients are, the fewer thebits that are required at a given quantization step size to representthe block after entropy coding.

Traditional intra coding such as known from, for example MPEG-2generation coding technologies, does not use intra prediction. However,some newer video compression technologies include techniques thatattempt, from, for example, surrounding sample data and/or metadataobtained during the encoding/decoding of spatially neighboring, andpreceding in decoding order, blocks of data. Such techniques arehenceforth called “intra prediction” techniques. Note that in at leastsome cases, intra prediction is only using reference data from thecurrent picture under reconstruction and not from reference pictures.

There can be many different forms of intra prediction. When more thanone of such techniques can be used in a given video coding technology,the technique in use can be coded in an intra prediction mode. Incertain cases, modes can have submodes and/or parameters, and those canbe coded individually or included in the mode codeword. Which codewordto use for a given mode/submode/parameter combination can have an impactin the coding efficiency gain through intra prediction, and so can theentropy coding technology used to translate the codewords into abitstream.

A certain mode of intra prediction was introduced with H.264, refined inH.265, and further refined in newer coding technologies such as jointexploration model (JEM), versatile video coding (VVC), and benchmark set(BMS). A predictor block can be formed using neighboring sample valuesbelonging to already available samples. Sample values of neighboringsamples are copied into the predictor block according to a direction. Areference to the direction in use can be coded in the bitstream or mayitself be predicted.

Motion compensation can be a lossy compression technique and can relateto techniques where a block of sample data from a previouslyreconstructed picture or part thereof (reference picture), after beingspatially shifted in a direction indicated by a motion vector (MVhenceforth), is used for the prediction of a newly reconstructed pictureor picture part. In some cases, the reference picture can be the same asthe picture currently under reconstruction. MVs can have two dimensionsX and Y, or three dimensions, the third being an indication of thereference picture in use (the latter, indirectly, can be a timedimension).

In some video compression techniques, an MV applicable to a certain areaof sample data can be predicted from other MVs, for example from thoserelated to another area of sample data spatially adjacent to the areaunder reconstruction, and preceding that MV in decoding order. Doing socan substantially reduce the amount of data required for coding the MV,thereby removing redundancy and increasing compression. MV predictioncan work effectively, for example, because when coding an input videosignal derived from a camera (known as natural video) there is astatistical likelihood that areas larger than the area to which a singleMV is applicable move in a similar direction and, therefore, can in somecases be predicted using a similar motion vector derived from MVs ofneighboring area. That results in the MV found for a given area to besimilar or the same as the MV predicted from the surrounding MVs, andthat in turn can be represented, after entropy coding, in a smallernumber of bits than what would be used if coding the MV directly. Insome cases, MV prediction can be an example of lossless compression of asignal (namely: the MVs) derived from the original signal (namely: thesample stream). In other cases, MV prediction itself can be lossy, forexample because of rounding errors when calculating a predictor fromseveral surrounding MVs.

Various MV prediction mechanisms are described in H.265/HEVC (ITU-T Rec.H.265, “High Efficiency Video Coding”, December 2016). Out of the manyMV prediction mechanisms that H.265 offers, described here is atechnique henceforth referred to as “spatial merge”.

Referring to FIG. 1, a current block (101) comprises samples that havebeen found by the encoder during the motion search process to bepredictable from a previous block of the same size that has beenspatially shifted. Instead of coding that MV directly, the MV can bederived from metadata associated with one or more reference pictures,for example from the most recent (in decoding order) reference picture,using the MV associated with either one of five surrounding samples,denoted A0, A1, and B0, B1, B2 (102 through 106, respectively). InH.265, the MV prediction can use predictors from the same referencepicture that the neighboring block is using.

SUMMARY

Aspects of the disclosure provide a first method of video decoding at avideo decoder. The method can include receiving a first high levelsyntax (HLS) element indicating whether an explicit multiple transformselection (MTS) is enabled or disabled for an intra coded block, andreceiving a second HLS element indicating whether the explicit MTS isenabled or disabled for an inter coded block. The first and second HLSelements control a same set of coding blocks that include the intracoded block and the inter coded block. An implicit MTS can be enabledfor the intra coded block when the first HLS element indicates theexplicit MTS is disabled for the intra coded block, and the second HLSelement indicates the explicit MTS is enabled for the inter coded block.

An embodiment of the method may further include applying the implicitMTS to the intra coded block. A transform type for processing the intracoded block can be determined according to a size of the intra codedblock. In various examples, the first or second HLS element can be oneof a video parameter set (VPS) syntax element, a sequence parameter set(SPS) syntax element, a picture parameter set (PPS) syntax element, aslice header syntax element, a tile header syntax element, or a tilegroup header syntax element. In an embodiment, the intra coded block isnot coded with an intra sub-partitioning (ISP) mode. In an embodiment,the method can further include receiving a third HLS element indicatingan MTS is enabled for each of the inter and intra coded blocks.

Aspects of the disclosure provide a second method of video decoding at avideo decoder. The second method can include receiving a first HLSelement indicating whether an MTS is enabled or disabled for an intracoded block, and receiving a second HLS element indicating whether anon-separable secondary transform (NSST) or matrix-based intraprediction (MIP) is disabled or enabled for the intra coded block. Animplicit MTS can be enabled for the intra coded block when the first HLSelement indicates the explicit MTS is disabled for the intra codedblock, and the second HLS element indicates the NSST or the MIP isdisabled for the intra coded block.

The disclosure can also provide a third method of video decoding at avideo decoder. The third method can include receiving an intra codedblock associated with a first block level syntax element indicatingwhether an MTS is applied, and a second block level syntax elementindicating whether an NSST is applied. An implicit MTS can be enabledfor the intra coded block when the first block level syntax elementindicates the MTS is not applied, and the second block level syntaxelement indicates the NSST is not applied.

Note that although the instant application refers to NSST, the disclosedmethods and systems can be applied to variants of NSST, such as, reducedsize transform (RST), and low-frequency non-separable secondarytransform (LFNST). Thus, NSST, RST, and/or LFNST can be usedinterchangeably throughout the instant application.

BRIEF DESCRIPTION OF THE DRAWINGS

Further features, the nature, and various advantages of the disclosedsubject matter will be more apparent from the following detaileddescription and the accompanying drawings in which:

FIG. 1 is a schematic illustration of a current block and itssurrounding spatial merge candidates in one example.

FIG. 2 is a schematic illustration of a simplified block diagram of acommunication system (200) in accordance with an embodiment.

FIG. 3 is a schematic illustration of a simplified block diagram of acommunication system (300) in accordance with an embodiment.

FIG. 4 is a schematic illustration of a simplified block diagram of adecoder in accordance with an embodiment.

FIG. 5 is a schematic illustration of a simplified block diagram of anencoder in accordance with an embodiment.

FIG. 6 shows a block diagram of an encoder in accordance with anotherembodiment.

FIG. 7 shows a block diagram of a decoder in accordance with anotherembodiment.

FIGS. 8A-8D show example transform core matrices of 4-point, 8-point,16-point, and 32-point DCT-2, respectively, according to an embodiment.

FIGS. 9A-9D show sub-block types, sizes, and positions supported insub-block transform (SBT) according to an embodiment.

FIG. 10 shows numbers of sub-partitions depending on the block size inan intra sub-partition (ISP) coding mode according to an embodiment.

FIG. 11 shows an example where a block is partitioned into twosub-partitions in an ISP coding mode.

FIG. 12 shows an example where a block is partitioned into foursub-partitions in an ISP coding mode.

FIGS. 13A-13E show a 64×64 transform core matrix of a 64-point DCT-2transform according to an embodiment.

FIG. 14 shows transform basis functions of DST/DCT transforms accordingto an embodiment.

FIG. 15 shows a table illustrating a mapping relationship between anmts_idx value and respective horizontal or vertical transforms accordingto an embodiment.

FIGS. 16A-16D show transform core matrices of a DST-7 transform typeaccording to an embodiment.

FIGS. 17A-17D show transform core matrices of a DCT-8 transform typeaccording to an embodiment.

FIG. 18 shows an example of controlling usage of multiple transformselection (MTS) using sequence parameter set (SPS) syntax elements.

FIG. 19 shows a table of mapping between intra prediction modes andtransform sets according to an embodiment.

FIGS. 20-21 show two alternative transform coding processes (2000) and(2100) for RST8×8 using 16×64 transform cores and 16×48 transform cores,respectively, according to an embodiment.

FIG. 22 shows an example CU-level syntax table (2200) where a syntaxelement lfnst_idx indicating a selection of a low frequencynon-separable secondary transform (LFNST) kernel is signaled at the endof CU-level syntax.

FIG. 23 shows a process (2301) of a reduced transform and a process(2302) of a reduced inverse transform according to an embodiment.

FIG. 24A shows the whole top-left 8×8 coefficients (shaded sub-blocks)of a residual block (2410) used as input for calculating a secondarytransform in RST8×8.

FIG. 24B shows the top-left three 4×4 sub-block coefficients (shadedsub-blocks) of the residual block (2410) used as input for calculating asecondary transform in RST8×8.

FIG. 25 shows a table for transform set selection based on an intraprediction mode according to an embodiment.

FIG. 26 shows an example process (2600) of a matrix-based intraprediction (MIP) mode.

FIG. 27 shows a CU-level syntax table where flags signaling matrix-basedintra prediction (MIP) modes are shown in a frame (2701) according to anembodiment.

FIGS. 28A-28B in combination show a text (2800) specifying a transformcoding process of performing explicit or implicit transform selectionfor a current block based on related syntax elements received from abitstream.

FIG. 29 shows modifications (2900) to the text (2800) that correspond toan implicit transform enabling scheme where implicit transform for intraresidual blocks and explicit transform for inter residual blocks cancoexist.

FIG. 30 shows modifications (3000) to the text (2800) that correspond toa scenario where an implicit transform is enabled when a non-separablesecondary transform (NSST) is disabled.

FIG. 31 shows modifications (3100) to the text (2800) that correspond toa scenario where an implicit transform is enabled when an MIP isdisabled.

FIG. 32 shows modifications (3200) to the text (2800) that correspond toa scenario where both MTS and NSST are not applied to a current block.

FIG. 33 shows modifications (3300) to the text (2800) that correspond toa scenario where none of MTS, NSST, or MIP is applied to a currentblock.

FIGS. 34-36 show flow charts of transform coding processes (3400),(3500), and (3600) according to some embodiments of the disclosure.

FIG. 37 is a schematic illustration of a computer system in accordancewith an embodiment.

DETAILED DESCRIPTION OF EMBODIMENTS

I. Video Coding Encoder and Decoder

FIG. 2 illustrates a simplified block diagram of a communication system(200) according to an embodiment of the present disclosure. Thecommunication system (200) includes a plurality of terminal devices thatcan communicate with each other, via, for example, a network (250). Forexample, the communication system (200) includes a first pair ofterminal devices (210) and (220) interconnected via the network (250).In the FIG. 2 example, the first pair of terminal devices (210) and(220) performs unidirectional transmission of data. For example, theterminal device (210) may code video data (e.g., a stream of videopictures that are captured by the terminal device (210)) fortransmission to the other terminal device (220) via the network (250).The encoded video data can be transmitted in the form of one or morecoded video bitstreams. The terminal device (220) may receive the codedvideo data from the network (250), decode the coded video data torecover the video pictures and display video pictures according to therecovered video data. Unidirectional data transmission may be common inmedia serving applications and the like.

In another example, the communication system (200) includes a secondpair of terminal devices (230) and (240) that performs bidirectionaltransmission of coded video data that may occur, for example, duringvideoconferencing. For bidirectional transmission of data, in anexample, each terminal device of the terminal devices (230) and (240)may code video data (e.g., a stream of video pictures that are capturedby the terminal device) for transmission to the other terminal device ofthe terminal devices (230) and (240) via the network (250). Eachterminal device of the terminal devices (230) and (240) also may receivethe coded video data transmitted by the other terminal device of theterminal devices (230) and (240), and may decode the coded video data torecover the video pictures and may display video pictures at anaccessible display device according to the recovered video data.

In the FIG. 2 example, the terminal devices (210), (220), (230) and(240) may be illustrated as servers, personal computers and smart phonesbut the principles of the present disclosure may be not so limited.Embodiments of the present disclosure find application with laptopcomputers, tablet computers, media players and/or dedicated videoconferencing equipment. The network (250) represents any number ofnetworks that convey coded video data among the terminal devices (210),(220), (230) and (240), including for example wireline (wired) and/orwireless communication networks. The communication network (250) mayexchange data in circuit-switched and/or packet-switched channels.Representative networks include telecommunications networks, local areanetworks, wide area networks and/or the Internet. For the purposes ofthe present discussion, the architecture and topology of the network(250) may be immaterial to the operation of the present disclosureunless explained herein below.

FIG. 3 illustrates, as an example for an application for the disclosedsubject matter, the placement of a video encoder and a video decoder ina streaming environment. The disclosed subject matter can be equallyapplicable to other video enabled applications, including, for example,video conferencing, digital TV, storing of compressed video on digitalmedia including CD, DVD, memory stick and the like, and so on.

A streaming system may include a capture subsystem (313), that caninclude a video source (301), for example a digital camera, creating forexample a stream of video pictures (302) that are uncompressed. In anexample, the stream of video pictures (302) includes samples that aretaken by the digital camera. The stream of video pictures (302),depicted as a bold line to emphasize a high data volume when compared toencoded video data (304) (or coded video bitstreams), can be processedby an electronic device (320) that includes a video encoder (303)coupled to the video source (301). The video encoder (303) can includehardware, software, or a combination thereof to enable or implementaspects of the disclosed subject matter as described in more detailbelow. The encoded video data (304) (or encoded video bitstream (304)),depicted as a thin line to emphasize the lower data volume when comparedto the stream of video pictures (302), can be stored on a streamingserver (305) for future use. One or more streaming client subsystems,such as client subsystems (306) and (308) in FIG. 3 can access thestreaming server (305) to retrieve copies (307) and (309) of the encodedvideo data (304). A client subsystem (306) can include a video decoder(310), for example, in an electronic device (330). The video decoder(310) decodes the incoming copy (307) of the encoded video data andcreates an outgoing stream of video pictures (311) that can be renderedon a display (312) (e.g., display screen) or other rendering device (notdepicted). In some streaming systems, the encoded video data (304),(307), and (309) (e.g., video bitstreams) can be encoded according tocertain video coding/compression standards. Examples of those standardsinclude ITU-T Recommendation H.265. In an example, a video codingstandard under development is informally known as Versatile Video Coding(VVC). The disclosed subject matter may be used in the context of VVC.

It is noted that the electronic devices (320) and (330) can includeother components (not shown). For example, the electronic device (320)can include a video decoder (not shown) and the electronic device (330)can include a video encoder (not shown) as well.

FIG. 4 shows a block diagram of a video decoder (410) according to anembodiment of the present disclosure. The video decoder (410) can beincluded in an electronic device (430). The electronic device (430) caninclude a receiver (431) (e.g., receiving circuitry). The video decoder(410) can be used in the place of the video decoder (310) in the FIG. 3example.

The receiver (431) may receive one or more coded video sequences to bedecoded by the video decoder (410); in the same or another embodiment,one coded video sequence at a time, where the decoding of each codedvideo sequence is independent from other coded video sequences. Thecoded video sequence may be received from a channel (401), which may bea hardware/software link to a storage device which stores the encodedvideo data. The receiver (431) may receive the encoded video data withother data, for example, coded audio data and/or ancillary data streams,that may be forwarded to their respective using entities (not depicted).The receiver (431) may separate the coded video sequence from the otherdata. To combat network jitter, a buffer memory (415) may be coupled inbetween the receiver (431) and an entropy decoder/parser (420) (“parser(420)” henceforth). In certain applications, the buffer memory (415) ispart of the video decoder (410). In others, it can be outside of thevideo decoder (410) (not depicted). In still others, there can be abuffer memory (not depicted) outside of the video decoder (410), forexample to combat network jitter, and in addition another buffer memory(415) inside the video decoder (410), for example to handle playouttiming. When the receiver (431) is receiving data from a store/forwarddevice of sufficient bandwidth and controllability, or from anisosynchronous network, the buffer memory (415) may not be needed, orcan be small. For use on best effort packet networks such as theInternet, the buffer memory (415) may be required, can be comparativelylarge and can be advantageously of adaptive size, and may at leastpartially be implemented in an operating system or similar elements (notdepicted) outside of the video decoder (410).

The video decoder (410) may include the parser (420) to reconstructsymbols (421) from the coded video sequence. Categories of those symbolsinclude information used to manage operation of the video decoder (410),and potentially information to control a rendering device such as arender device (412) (e.g., a display screen) that is not an integralpart of the electronic device (430) but can be coupled to the electronicdevice (430), as was shown in FIG. 4. The control information for therendering device(s) may be in the form of Supplemental EnhancementInformation (SEI messages) or Video Usability Information (VUI)parameter set fragments (not depicted). The parser (420) mayparse/entropy-decode the coded video sequence that is received. Thecoding of the coded video sequence can be in accordance with a videocoding technology or standard, and can follow various principles,including variable length coding, Huffman coding, arithmetic coding withor without context sensitivity, and so forth. The parser (420) mayextract from the coded video sequence, a set of subgroup parameters forat least one of the subgroups of pixels in the video decoder, based uponat least one parameter corresponding to the group. Subgroups can includeGroups of Pictures (GOPs), pictures, tiles, slices, macroblocks, CodingUnits (CUs), blocks, Transform Units (TUs), Prediction Units (PUs) andso forth. The parser (420) may also extract from the coded videosequence information such as transform coefficients, quantizer parametervalues, motion vectors, and so forth.

The parser (420) may perform an entropy decoding/parsing operation onthe video sequence received from the buffer memory (415), so as tocreate symbols (421).

Reconstruction of the symbols (421) can involve multiple different unitsdepending on the type of the coded video picture or parts thereof (suchas: inter and intra picture, inter and intra block), and other factors.Which units are involved, and how, can be controlled by the subgroupcontrol information that was parsed from the coded video sequence by theparser (420). The flow of such subgroup control information between theparser (420) and the multiple units below is not depicted for clarity.

Beyond the functional blocks already mentioned, the video decoder (410)can be conceptually subdivided into a number of functional units asdescribed below. In a practical implementation operating undercommercial constraints, many of these units interact closely with eachother and can, at least partly, be integrated into each other. However,for the purpose of describing the disclosed subject matter, theconceptual subdivision into the functional units below is appropriate.

A first unit is the scaler/inverse transform unit (451). Thescaler/inverse transform unit (451) receives a quantized transformcoefficient as well as control information, including which transform touse, block size, quantization factor, quantization scaling matrices,etc. as symbol(s) (421) from the parser (420). The scaler/inversetransform unit (451) can output blocks comprising sample values, thatcan be input into aggregator (455).

In some cases, the output samples of the scaler/inverse transform (451)can pertain to an intra coded block; that is: a block that is not usingpredictive information from previously reconstructed pictures, but canuse predictive information from previously reconstructed parts of thecurrent picture. Such predictive information can be provided by an intrapicture prediction unit (452). In some cases, the intra pictureprediction unit (452) generates a block of the same size and shape ofthe block under reconstruction, using surrounding already reconstructedinformation fetched from the current picture buffer (458). The currentpicture buffer (458) buffers, for example, partly reconstructed currentpicture and/or fully reconstructed current picture. The aggregator(455), in some cases, adds, on a per sample basis, the predictioninformation the intra prediction unit (452) has generated to the outputsample information as provided by the scaler/inverse transform unit(451).

In other cases, the output samples of the scaler/inverse transform unit(451) can pertain to an inter coded, and potentially motion compensatedblock. In such a case, a motion compensation prediction unit (453) canaccess reference picture memory (457) to fetch samples used forprediction. After motion compensating the fetched samples in accordancewith the symbols (421) pertaining to the block, these samples can beadded by the aggregator (455) to the output of the scaler/inversetransform unit (451) (in this case called the residual samples orresidual signal) so as to generate output sample information. Theaddresses within the reference picture memory (457) from where themotion compensation prediction unit (453) fetches prediction samples canbe controlled by motion vectors, available to the motion compensationprediction unit (453) in the form of symbols (421) that can have, forexample X, Y, and reference picture components. Motion compensation alsocan include interpolation of sample values as fetched from the referencepicture memory (457) when sub-sample exact motion vectors are in use,motion vector prediction mechanisms, and so forth.

The output samples of the aggregator (455) can be subject to variousloop filtering techniques in the loop filter unit (456). Videocompression technologies can include in-loop filter technologies thatare controlled by parameters included in the coded video sequence (alsoreferred to as coded video bitstream) and made available to the loopfilter unit (456) as symbols (421) from the parser (420), but can alsobe responsive to meta-information obtained during the decoding ofprevious (in decoding order) parts of the coded picture or coded videosequence, as well as responsive to previously reconstructed andloop-filtered sample values.

The output of the loop filter unit (456) can be a sample stream that canbe output to the render device (412) as well as stored in the referencepicture memory (457) for use in future inter-picture prediction.

Certain coded pictures, once fully reconstructed, can be used asreference pictures for future prediction. For example, once a codedpicture corresponding to a current picture is fully reconstructed andthe coded picture has been identified as a reference picture (by, forexample, the parser (420)), the current picture buffer (458) can becomea part of the reference picture memory (457), and a fresh currentpicture buffer can be reallocated before commencing the reconstructionof the following coded picture.

The video decoder (410) may perform decoding operations according to apredetermined video compression technology in a standard, such as ITU-TRec. H.265. The coded video sequence may conform to a syntax specifiedby the video compression technology or standard being used, in the sensethat the coded video sequence adheres to both the syntax of the videocompression technology or standard and the profiles as documented in thevideo compression technology or standard. Specifically, a profile canselect certain tools as the only tools available for use under thatprofile from all the tools available in the video compression technologyor standard. Also necessary for compliance can be that the complexity ofthe coded video sequence is within bounds as defined by the level of thevideo compression technology or standard. In some cases, levels restrictthe maximum picture size, maximum frame rate, maximum reconstructionsample rate (measured in, for example megasamples per second), maximumreference picture size, and so on. Limits set by levels can, in somecases, be further restricted through Hypothetical Reference Decoder(HRD) specifications and metadata for HRD buffer management signaled inthe coded video sequence.

In an embodiment, the receiver (431) may receive additional (redundant)data with the encoded video. The additional data may be included as partof the coded video sequence(s). The additional data may be used by thevideo decoder (410) to properly decode the data and/or to moreaccurately reconstruct the original video data. Additional data can bein the form of, for example, temporal, spatial, or signal noise ratio(SNR) enhancement layers, redundant slices, redundant pictures, forwarderror correction codes, and so on.

FIG. 5 shows a block diagram of a video encoder (503) according to anembodiment of the present disclosure. The video encoder (503) isincluded in an electronic device (520). The electronic device (520)includes a transmitter (540) (e.g., transmitting circuitry). The videoencoder (503) can be used in the place of the video encoder (303) in theFIG. 3 example.

The video encoder (503) may receive video samples from a video source(501) (that is not part of the electronic device (520) in the FIG. 5example) that may capture video image(s) to be coded by the videoencoder (503). In another example, the video source (501) is a part ofthe electronic device (520).

The video source (501) may provide the source video sequence to be codedby the video encoder (503) in the form of a digital video sample streamthat can be of any suitable bit depth (for example: 8 bit, 10 bit, 12bit, . . . ), any colorspace (for example, BT.601 Y CrCB, RGB, . . . ),and any suitable sampling structure (for example Y CrCb 4:2:0, Y CrCb4:4:4). In a media serving system, the video source (501) may be astorage device storing previously prepared video. In a videoconferencingsystem, the video source (501) may be a camera that captures local imageinformation as a video sequence. Video data may be provided as aplurality of individual pictures that impart motion when viewed insequence. The pictures themselves may be organized as a spatial array ofpixels, wherein each pixel can comprise one or more samples depending onthe sampling structure, color space, etc. in use. A person skilled inthe art can readily understand the relationship between pixels andsamples. The description below focuses on samples.

According to an embodiment, the video encoder (503) may code andcompress the pictures of the source video sequence into a coded videosequence (543) in real time or under any other time constraints asrequired by the application. Enforcing appropriate coding speed is onefunction of a controller (550). In some embodiments, the controller(550) controls other functional units as described below and isfunctionally coupled to the other functional units. The coupling is notdepicted for clarity. Parameters set by the controller (550) can includerate control related parameters (picture skip, quantizer, lambda valueof rate-distortion optimization techniques, . . . ), picture size, groupof pictures (GOP) layout, maximum motion vector search range, and soforth. The controller (550) can be configured to have other suitablefunctions that pertain to the video encoder (503) optimized for acertain system design.

In some embodiments, the video encoder (503) is configured to operate ina coding loop. As an oversimplified description, in an example, thecoding loop can include a source coder (530) (e.g., responsible forcreating symbols, such as a symbol stream, based on an input picture tobe coded, and a reference picture(s)), and a (local) decoder (533)embedded in the video encoder (503). The decoder (533) reconstructs thesymbols to create the sample data in a similar manner as a (remote)decoder also would create (as any compression between symbols and codedvideo bitstream is lossless in the video compression technologiesconsidered in the disclosed subject matter). The reconstructed samplestream (sample data) is input to the reference picture memory (534). Asthe decoding of a symbol stream leads to bit-exact results independentof decoder location (local or remote), the content in the referencepicture memory (534) is also bit exact between the local encoder andremote encoder. In other words, the prediction part of an encoder “sees”as reference picture samples exactly the same sample values as a decoderwould “see” when using prediction during decoding. This fundamentalprinciple of reference picture synchronicity (and resulting drift, ifsynchronicity cannot be maintained, for example because of channelerrors) is used in some related arts as well.

The operation of the “local” decoder (533) can be the same as of a“remote” decoder, such as the video decoder (410), which has alreadybeen described in detail above in conjunction with FIG. 4. Brieflyreferring also to FIG. 4, however, as symbols are available andencoding/decoding of symbols to a coded video sequence by an entropycoder (545) and the parser (420) can be lossless, the entropy decodingparts of the video decoder (410), including the buffer memory (415), andparser (420) may not be fully implemented in the local decoder (533).

An observation that can be made at this point is that any decodertechnology except the parsing/entropy decoding that is present in adecoder also necessarily needs to be present, in substantially identicalfunctional form, in a corresponding encoder. For this reason, thedisclosed subject matter focuses on decoder operation. The descriptionof encoder technologies can be abbreviated as they are the inverse ofthe comprehensively described decoder technologies. Only in certainareas a more detail description is required and provided below.

During operation, in some examples, the source coder (530) may performmotion compensated predictive coding, which codes an input picturepredictively with reference to one or more previously-coded picture fromthe video sequence that were designated as “reference pictures”. In thismanner, the coding engine (532) codes differences between pixel blocksof an input picture and pixel blocks of reference picture(s) that may beselected as prediction reference(s) to the input picture.

The local video decoder (533) may decode coded video data of picturesthat may be designated as reference pictures, based on symbols createdby the source coder (530). Operations of the coding engine (532) mayadvantageously be lossy processes. When the coded video data may bedecoded at a video decoder (not shown in FIG. 5), the reconstructedvideo sequence typically may be a replica of the source video sequencewith some errors. The local video decoder (533) replicates decodingprocesses that may be performed by the video decoder on referencepictures and may cause reconstructed reference pictures to be stored inthe reference picture cache (534). In this manner, the video encoder(503) may store copies of reconstructed reference pictures locally thathave common content as the reconstructed reference pictures that will beobtained by a far-end video decoder (absent transmission errors).

The predictor (535) may perform prediction searches for the codingengine (532). That is, for a new picture to be coded, the predictor(535) may search the reference picture memory (534) for sample data (ascandidate reference pixel blocks) or certain metadata such as referencepicture motion vectors, block shapes, and so on, that may serve as anappropriate prediction reference for the new pictures. The predictor(535) may operate on a sample block-by-pixel block basis to findappropriate prediction references. In some cases, as determined bysearch results obtained by the predictor (535), an input picture mayhave prediction references drawn from multiple reference pictures storedin the reference picture memory (534).

The controller (550) may manage coding operations of the source coder(530), including, for example, setting of parameters and subgroupparameters used for encoding the video data.

Output of all aforementioned functional units may be subjected toentropy coding in the entropy coder (545). The entropy coder (545)translates the symbols as generated by the various functional units intoa coded video sequence, by lossless compressing the symbols according totechnologies such as Huffman coding, variable length coding, arithmeticcoding, and so forth.

The transmitter (540) may buffer the coded video sequence(s) as createdby the entropy coder (545) to prepare for transmission via acommunication channel (560), which may be a hardware/software link to astorage device which would store the encoded video data. The transmitter(540) may merge coded video data from the video coder (503) with otherdata to be transmitted, for example, coded audio data and/or ancillarydata streams (sources not shown).

The controller (550) may manage operation of the video encoder (503).During coding, the controller (550) may assign to each coded picture acertain coded picture type, which may affect the coding techniques thatmay be applied to the respective picture. For example, pictures oftenmay be assigned as one of the following picture types:

An Intra Picture (I picture) may be one that may be coded and decodedwithout using any other picture in the sequence as a source ofprediction. Some video codecs allow for different types of intrapictures, including, for example Independent Decoder Refresh (“IDR”)Pictures. A person skilled in the art is aware of those variants of Ipictures and their respective applications and features.

A predictive picture (P picture) may be one that may be coded anddecoded using intra prediction or inter prediction using at most onemotion vector and reference index to predict the sample values of eachblock.

A bi-directionally predictive picture (B Picture) may be one that may becoded and decoded using intra prediction or inter prediction using atmost two motion vectors and reference indices to predict the samplevalues of each block. Similarly, multiple-predictive pictures can usemore than two reference pictures and associated metadata for thereconstruction of a single block.

Source pictures commonly may be subdivided spatially into a plurality ofsample blocks (for example, blocks of 4×4, 8×8, 4×8, or 16×16 sampleseach) and coded on a block-by-block basis. Blocks may be codedpredictively with reference to other (already coded) blocks asdetermined by the coding assignment applied to the blocks' respectivepictures. For example, blocks of I pictures may be codednon-predictively or they may be coded predictively with reference toalready coded blocks of the same picture (spatial prediction or intraprediction). Pixel blocks of P pictures may be coded predictively, viaspatial prediction or via temporal prediction with reference to onepreviously coded reference picture. Blocks of B pictures may be codedpredictively, via spatial prediction or via temporal prediction withreference to one or two previously coded reference pictures.

The video encoder (503) may perform coding operations according to apredetermined video coding technology or standard, such as ITU-T Rec.H.265. In its operation, the video encoder (503) may perform variouscompression operations, including predictive coding operations thatexploit temporal and spatial redundancies in the input video sequence.The coded video data, therefore, may conform to a syntax specified bythe video coding technology or standard being used.

In an embodiment, the transmitter (540) may transmit additional datawith the encoded video. The source coder (530) may include such data aspart of the coded video sequence. Additional data may comprisetemporal/spatial/SNR enhancement layers, other forms of redundant datasuch as redundant pictures and slices, SEI messages, VUI parameter setfragments, and so on.

A video may be captured as a plurality of source pictures (videopictures) in a temporal sequence. Intra-picture prediction (oftenabbreviated to intra prediction) makes use of spatial correlation in agiven picture, and inter-picture prediction makes uses of the (temporalor other) correlation between the pictures. In an example, a specificpicture under encoding/decoding, which is referred to as a currentpicture, is partitioned into blocks. When a block in the current pictureis similar to a reference block in a previously coded and still bufferedreference picture in the video, the block in the current picture can becoded by a vector that is referred to as a motion vector. The motionvector points to the reference block in the reference picture, and canhave a third dimension identifying the reference picture, in casemultiple reference pictures are in use.

In some embodiments, a bi-prediction technique can be used in theinter-picture prediction. According to the bi-prediction technique, tworeference pictures, such as a first reference picture and a secondreference picture that are both prior in decoding order to the currentpicture in the video (but may be in the past and future, respectively,in display order) are used. A block in the current picture can be codedby a first motion vector that points to a first reference block in thefirst reference picture, and a second motion vector that points to asecond reference block in the second reference picture. The block can bepredicted by a combination of the first reference block and the secondreference block.

Further, a merge mode technique can be used in the inter-pictureprediction to improve coding efficiency.

According to some embodiments of the disclosure, predictions, such asinter-picture predictions and intra-picture predictions are performed inthe unit of blocks. For example, according to the HEVC standard, apicture in a sequence of video pictures is partitioned into coding treeunits (CTU) for compression, the CTUs in a picture have the same size,such as 64×64 pixels, 32×32 pixels, or 16×16 pixels. In general, a CTUincludes three coding tree blocks (CTBs), which are one luma CTB and twochroma CTBs. Each CTU can be recursively quadtree split into one ormultiple coding units (CUs). For example, a CTU of 64×64 pixels can besplit into one CU of 64×64 pixels, or 4 CUs of 32×32 pixels, or 16 CUsof 16×16 pixels. In an example, each CU is analyzed to determine aprediction type for the CU, such as an inter prediction type or an intraprediction type. The CU is split into one or more prediction units (PUs)depending on the temporal and/or spatial predictability. Generally, eachPU includes a luma prediction block (PB), and two chroma. PBs. In anembodiment, a prediction operation in coding (encoding/decoding) isperformed in the unit of a prediction block. Using a luma predictionblock as an example of a prediction block, the prediction block includesa matrix of values (e.g., luma values) for pixels, such as 8×8 pixels,16×16 pixels, 8×16 pixels, 16×8 pixels, and the like.

FIG. 6 shows a diagram of a video encoder (603) according to anotherembodiment of the disclosure. The video encoder (603) is configured toreceive a processing block (e.g., a prediction block) of sample valueswithin a current video picture in a sequence of video pictures, andencode the processing block into a coded picture that is part of a codedvideo sequence. In an example, the video encoder (603) is used in theplace of the video encoder (303) in the FIG. 3 example.

In an HEVC example, the video encoder (603) receives a matrix of samplevalues for a processing block, such as a prediction block of 8×8samples, and the like. The video encoder (603) determines whether theprocessing block is best coded using intra mode, inter mode, orbi-prediction mode using, for example, rate-distortion optimization.When the processing block is to be coded in intra mode, the videoencoder (603) may use an intra prediction technique to encode theprocessing block into the coded picture; and when the processing blockis to be coded in inter mode or bi-prediction mode, the video encoder(603) may use an inter prediction or bi-prediction technique,respectively, to encode the processing block into the coded picture. Incertain video coding technologies, merge mode can be an inter pictureprediction submode where the motion vector is derived from one or moremotion vector predictors without the benefit of a coded motion vectorcomponent outside the predictors. In certain other video codingtechnologies, a motion vector component applicable to the subject blockmay be present. In an example, the video encoder (603) includes othercomponents, such as a mode decision module (not shown) to determine themode of the processing blocks.

In the FIG. 6 example, the video encoder (603) includes the interencoder (630), an intra encoder (622), a residue calculator (623), aswitch (626), a residue encoder (624), a general controller (621), andan entropy encoder (625) coupled together as shown in FIG. 6.

The inter encoder (630) is configured to receive the samples of thecurrent block (e.g., a processing block), compare the block to one ormore reference blocks in reference pictures (e.g., blocks in previouspictures and later pictures), generate inter prediction information(e.g., description of redundant information according to inter encodingtechnique, motion vectors, merge mode information), and calculate interprediction results (e.g., predicted block) based on the inter predictioninformation using any suitable technique. In some examples, thereference pictures are decoded reference pictures that are decoded basedon the encoded video information.

The intra encoder (622) is configured to receive the samples of thecurrent block (e.g., a processing block), in some cases compare theblock to blocks already coded in the same picture, generate quantizedcoefficients after transform, and in some cases also intra predictioninformation (e.g., an intra prediction direction information accordingto one or more intra encoding techniques). In an example, the intraencoder (622) also calculates intra prediction results (e.g., predictedblock) based on the intra prediction information and reference blocks inthe same picture.

The general controller (621) is configured to determine general controldata and control other components of the video encoder (603) based onthe general control data. In an example, the general controller (621)determines the mode of the block, and provides a control signal to theswitch (626) based on the mode. For example, when the mode is the intramode, the general controller (621) controls the switch (626) to selectthe intra mode result for use by the residue calculator (623), andcontrols the entropy encoder (625) to select the intra predictioninformation and include the intra prediction information in thebitstream; and when the mode is the inter mode, the general controller(621) controls the switch (626) to select the inter prediction resultfor use by the residue calculator (623), and controls the entropyencoder (625) to select the inter prediction information and include theinter prediction information in the bitstream.

The residue calculator (623) is configured to calculate a difference(residue data) between the received block and prediction resultsselected from the intra encoder (622) or the inter encoder (630). Theresidue encoder (624) is configured to operate based on the residue datato encode the residue data to generate the transform coefficients. In anexample, the residue encoder (624) is configured to convert the residuedata from a spatial domain to a frequency domain, and generate thetransform coefficients. The transform coefficients are then subject toquantization processing to obtain quantized transform coefficients. Invarious embodiments, the video encoder (603) also includes a residuedecoder (628). The residue decoder (628) is configured to performinverse-transform, and generate the decoded residue data. The decodedresidue data can be suitably used by the intra encoder (622) and theinter encoder (630). For example, the inter encoder (630) can generatedecoded blocks based on the decoded residue data and inter predictioninformation, and the intra encoder (622) can generate decoded blocksbased on the decoded residue data and the intra prediction information.The decoded blocks are suitably processed to generate decoded picturesand the decoded pictures can be buffered in a memory circuit (not shown)and used as reference pictures in some examples.

The entropy encoder (625) is configured to format the bitstream toinclude the encoded block. The entropy encoder (625) is configured toinclude various information according to a suitable standard, such asthe HEVC standard. In an example, the entropy encoder (625) isconfigured to include the general control data, the selected predictioninformation (e.g., intra prediction information or inter predictioninformation), the residue information, and other suitable information inthe bitstream. Note that, according to the disclosed subject matter,when coding a block in the merge submode of either inter mode orbi-prediction mode, there is no residue information.

FIG. 7 shows a diagram of a video decoder (710) according to anotherembodiment of the disclosure. The video decoder (710) is configured toreceive coded pictures that are part of a coded video sequence, anddecode the coded pictures to generate reconstructed pictures. In anexample, the video decoder (710) is used in the place of the videodecoder (310) in the FIG. 3 example.

In the FIG. 7 example, the video decoder (710) includes an entropydecoder (771), an inter decoder (780), a residue decoder (773), areconstruction module (774), and an intra decoder (772) coupled togetheras shown in FIG. 7.

The entropy decoder (771) can be configured to reconstruct, from thecoded picture, certain symbols that represent the syntax elements ofwhich the coded picture is made up. Such symbols can include, forexample, the mode in which a block is coded (such as, for example, intramode, inter mode, bi-predicted mode, the latter two in merge submode oranother submode), prediction information (such as, for example, intraprediction information or inter prediction information) that canidentify certain sample or metadata that is used for prediction by theintra decoder (772) or the inter decoder (780), respectively, residualinformation in the form of, for example, quantized transformcoefficients, and the like. In an example, when the prediction mode isinter or bi-predicted mode, the inter prediction information is providedto the inter decoder (780); and when the prediction type is the intraprediction type, the intra prediction information is provided to theintra decoder (772). The residual information can be subject to inversequantization and is provided to the residue decoder (773).

The inter decoder (780) is configured to receive the inter predictioninformation, and generate inter prediction results based on the interprediction information.

The intra decoder (772) is configured to receive the intra predictioninformation, and generate prediction results based on the intraprediction information.

The residue decoder (773) is configured to perform inverse quantizationto extract de-quantized transform coefficients, and process thede-quantized transform coefficients to convert the residual from thefrequency domain to the spatial domain. The residue decoder (773) mayalso require certain control information (to include the QuantizerParameter (QP)), and that information may be provided by the entropydecoder (771) (data path not depicted as this may be low volume controlinformation only).

The reconstruction module (774) is configured to combine, in the spatialdomain, the residual as output by the residue decoder (773) and theprediction results (as output by the inter or intra prediction modulesas the case may be) to form a reconstructed block, that may be part ofthe reconstructed picture, which in turn may be part of thereconstructed video. It is noted that other suitable operations, such asa deblocking operation and the like, can be performed to improve thevisual quality.

It is noted that the video encoders (303), (503), and (603), and thevideo decoders (310), (410), and (710) can be implemented using anysuitable technique. In an embodiment, the video encoders (303), (503),and (603), and the video decoders (310), (410), and (710) can beimplemented using one or more integrated circuits. In anotherembodiment, the video encoders (303), (503), and (503), and the videodecoders (310), (410), and (710) can be implemented using one or moreprocessors that execute software instructions.

II. Transform Coding Techniques and Related Techniques

1. DCT-2 Primary Transform Examples

In some embodiments, 4-point, 8-point, 16-point and 32-point DCT-2transforms are used as primary transforms. FIGS. 8A-8D show transformcore matrices of 4-point, 8-point, 16-point, and 32-point DCT-2,respectively. Elements of those transform core matrices can berepresented using 8-bit integers, and thus those transform core matricesare referred to as 8-bit transform cores. As shown, the transform corematrix of a smaller DCT-2 is a part of that of a larger DCT-2.

The DCT-2 core matrices show symmetry/anti-symmetry characteristics.Accordingly, a so-called “partial butterfly” implementation can besupported to reduce the number of operation counts (multiplications,adds/subs, shifts). Identical results of matrix multiplication can beobtained using the partial butterfly implementation compared with thatthe partial butterfly implementation is not used.

2. Sub-Block Transform Coding Examples

2.1 Sub-Block Transform (SBT)

In some embodiments, a sub-block transform (SBT), also referred to asspatially varying transform (SVT), is employed. The SBT is applied tointer prediction residuals in some embodiments. For example, a codingblock can be partitioned into sub-blocks, only part of the sub-blocks istreated at a residual block. Zero residual is assumed for the remainingpart of the sub-blocks. Therefore, the residual block is smaller thanthe coding block, and a transform size in SBT is smaller than the codingblock size. For the region which is not covered by the residual block,no transform processing is performed.

FIGS. 9A-9D show sub-block types (SVT-H, SVT-V) (e.g., vertically orhorizontally partitioned), sizes and positions (e.g., left half, leftquarter, right half, right quarter, top half, top quarter, bottom half,bottom quarter) supported in SBT. The shaded regions labeled by letter“A” are residual blocks to be transform-coded, and the other regions areassumed to be zero residual without transform.

2.2. Intra Sub-Partition (ISP) Coding Mode

In some embodiments, an intra sub-partition (ISP) coding mode isemployed. In ISP coding mode, a luma intra-predicted block can bepartitioned vertically or horizontally into 2 or 4 sub-partitions. Thenumber of sub-partitions can depend on a size of the block. FIG. 10shows numbers of sub-partitions depending on the block size. FIG. 11shows a scenario where a block is partitioned into two sub-partitions.FIG. 12 shows a scenario where a block is partitioned into foursub-partitions. In an example, all sub-partitions fulfill a condition ofhaving at least 16 samples. In an example, ISP is not applied to chromacomponents.

In an example, for each of sub-partitions partitioned from a codingblock, a residual signal is generated by entropy decoding respectivecoefficients sent from an encoder and then inverse quantizing andinverse transforming them. Then, a first one of the sub-partitions isintra predicted to generate a prediction signal. The prediction signalis added to the respective residual signal of the first sub-partition toobtain corresponding reconstructed samples. Thereafter, thereconstructed sample values of the first sub-partition can be availableto generate a prediction of a second one of the sub-partitions. Thisprocess can be repeated sub-partition by sub-partition, until allsub-partitions from the coding block are reconstructed. In an example,all the sub-partitions share a same intra mode.

In an embodiment, the ISP coding mode is only tested with intra modesthat are part of a most probable mode (MPM) list. Accordingly, if ablock uses ISP, then a MPM flag can be inferred to be one. In addition,when ISP is used for a certain block, then a respective MPM list will bemodified to exclude DC mode and to prioritize horizontal intra modes forthe ISP horizontal split and vertical intra modes for the vertical one.

In ISP coding mode, each sub-partition can be regarded as a sub-TU,since the transform and reconstruction is performed individually foreach sub-partition.

3. Transform Coding with Expanded DCT-2 Transforms and MultipleTransform Selection (MTS)

In some embodiments, when both the height and width of a coding block issmaller than or equal to 64 samples, a transform size is always the sameas a coding block size. When either the height or width of to codingblock is larger than 64 samples, when performing transform or intraprediction, the coding block is further split into multiple sub-blocks,where the width and height of each sub-block is smaller than or equal to64, and transform processing is performed on each sub-block.

3.1 Transform Coding with Expanded DCT-2 Transforms

In some embodiments, in addition to 4-point, 8-point, 16-point and32-point DCT-2 transforms described above, 2-point and 64-point DCT-2transform can be used. FIGS. 13A-13E show a 64×64 transform core matrixof the 64-point DCT-2 transform.

3.2 Explicitly Signaled Transform

In some embodiments, in addition to DCT-2 and 4×4 DST-7 transformcoding, a multiple transform selection (MTS) (also known as enhancedmultiple transform (EMT), or adaptive multiple transform (AMT)) can beused for residual coding of both inter and intra coded blocks. The MTSuses multiple selected transforms from discrete cosine transform(DCT)/discrete sine transform (DST) families other than the DCT-2 and4×4 DST-7 transforms. The selection can be performed at an encoder andexplicitly signaled from the encoder to a decoder. For example, theselected transforms can include DST-7, or DCT-8 transforms. FIG. 14shows transform basis functions of DST/DCT transforms. In someembodiments, the DST/DCT transform core matrices used in MTS arerepresented with 8-bit representation.

In some embodiments, MTS can be applied to CUs with both a width andheight smaller than or equal to 32 samples. Whether to apply MTS or notcan be controlled by a flag denoted by mts_flag. For example, when themts_flag is equal to 0, only DCT-2 is applied to coding a residue block.When the mts_flag is equal to 1, which indicates MTS is applied,selected transforms can be used. For example, an index, denoted bymts_idx, can further be signaled using 2 bins to specify a horizontaland vertical transforms to be used.

FIG. 15 shows a table (1500) illustrating a mapping relationship betweenan mts_idx value and respective horizontal or vertical transforms. Therow (1301) with the mts_idx having a value of −1 corresponds to ascenario where the mts_flag is equal to 0 (which indicates MTS is notapplied), and DCT-2 transform is used. The rows (1302)-(1305) with themts_idx having a value of 0, 1, 2, or 3 corresponding to a scenariowhere the mts_flag is equal to 1 (which indicate MTS is applied). In theright two columns of the table (1500), 0 represents a transform type ofDCT-2, 1 represents a transform type of DST-7, and 2 represents atransform type of DCT-8.

FIGS. 16A-16D show transform core matrices of a DST-7 transform type.FIGS. 17A-17D show transform core matrices of a DCT-8 transform type.

In some embodiments, MTS can be enabled or disabled using high levelsyntax (HLS) elements. Each of the HLS elements can be a video parameterset (VPS) syntax element, a sequence parameter set (SPS) syntax element,a picture parameter set (PPS) syntax element, a slice header syntaxelement, a tile header syntax element, or a tile group header syntaxelement, and the like. FIG. 18 shows an example of controlling usage ofMTS using SPS syntax elements. As shown, an SPS syntax element,sps_mts_enabled_flag, can be signaled to indicate whether an MTS isenabled for a video sequence. When the MTS is enabled, two syntaxelements, sps_explicit_mts_intra_enabled_flag andsps_explicit_mts_inter_enabled_flag, can be signaled to indicate whetherthe MTS is enabled for coding inter or intra predicted blocks,respectively.

In an embodiment, an implicit MTS is applied in case the above signalingbased MTS (referred to as explicit MIS) is not used. With the implicitMTS, a transform selection can be made according to a block width andheight instead of based on signaling. For example, with an implicit MTS,a DST-7 transform can be selected for a shorter side of a transformblock and a DCT-2 transform can be selected for a longer side of thetransform block.

3.3 Scenarios where Implicit Transform Selection is Applied

In various embodiments, for certain scenarios, DST-7 and/or DCT-8 can beused without being explicitly signaled. For example, DST-7 and/or DCT-8can be used implicitly based on information that is available for bothan encoder and a corresponding decoder. These scenarios include:

3.3.1 Intra Sub-Partitioning (ISP)

For a residual block coded with an ISP mode, a horizontal transform isselected as DST-7 as long as a block width of the residual block isgreater than or equal to 4 and less than or equal to 16, and a verticaltransform is selected as DST-7 as long as a block height of the residualblock is greater than or equal to 4 and less than or equal to 16.

3.3.2 Sub-Block Transform (SBT)

For an SBT mode, for a sub-TU located at the left half (or quarter) orright half (or quarter) of a current CU, the horizontal transform can beDCT-8 or DST-7, respectively. Otherwise (a sub-TU has a same width witha current CU), DCT-2 can be used sued. For a sub-TU located at the tophalf (or quarter) or bottom half (or quarter) of a current CU, thevertical transform can be DCT-8 or DST-7, respectively. Otherwise (asub-TU has a same height with a current CU), DCT-2 can be used.

3.3.3 MTS Disabled By HLS Elements

For example, when the sps_mts_enabled_flag is signaled as true, but boththe sps_explicit_mts_intra_enabled_flag andsps_explicit_mts_inter_enabled_flag are signaled as false, for intraprediction residuals, a horizontal transform can be selected as DST-7 aslong as a respective block width is greater than or equal to 4 and lessthan or equal to 16, and a vertical transform can be selected as DST-7as long as a respective block height is greater than or equal to 4 andless than or equal to 16.

4. Non-Separable Secondary Transform (NSST)

4.1 Initial Design of NSST

In some embodiments, a mode-dependent non-separable secondary transform(NSST) can be applied between a forward core transform and quantization(at an encoder) and between a de-quantization and inverse core transform(at a corresponding decoder). To keep low complexity, an NSST can onlybe applied to low frequency coefficients after the primary transform insome embodiments. If both a width (W) and a height (H) of a transformcoefficient block is larger than or equal to 8, then 8×8 non-separablesecondary transform can be applied to a top-left 8×8 region of thetransform coefficients block. Otherwise, if either W or H of a transformcoefficient block is equal to 4, a 4×4 non-separable secondary transformcan be applied and the 4×4 non-separable transform is performed on thetop-left min(8, W)×min(8, H) region of the transform coefficient block.The above transform selection rule is applied for both luma and chromacomponents.

Matrix multiplication implementation of a non-separable transform isdescribed as follows using a 4×4 input block as an example. To apply thenon-separable transform, the 4×4 input block X

$\begin{matrix}{X = \begin{bmatrix}X_{00} & X_{01} & X_{03} \\X_{10} & X_{12} & X_{13} \\X_{20} & X_{22} & X_{23} \\X_{30} & X_{32} & X_{33}\end{bmatrix}} & \left( {{Eq}.\mspace{11mu} 1} \right)\end{matrix}$

is represented as a vector

:

{right arrow over (X)}=[X ₀₀ X ₀₁ X ₀₂ X ₀₃ X ₁₀ X ₁₁ X ₁₂ X ₁₃ X ₂₀ X₂₁ X ₂₂ X ₂₃ X ₃₀ X ₃₁ X ₃₂ X ₃₃]^(T)   (Eq. 2)

The non-separable transform is calculated as,

=T·

,  (Eq. 3)

where

indicates the transform coefficient vector, and T is a 16×16 transformmatrix. The 16×1 coefficient vector

is subsequently re-organized as a 4×4 block using a scanning order forthat block (horizontal, vertical or diagonal). The coefficients withsmaller index will be placed with the smaller scanning index in the 4×4coefficient block. In an example, a hypercube-givens transform (HyGT)with butterfly implementation is used instead of matrix multiplicationto reduce the complexity of non-separable transform.

In an example of NSST, there can be totally 35×3 non-separable secondarytransforms for both 4×4 and 8×8 block size, where 35 is the number oftransform sets each corresponding to an intra prediction mode, and 3 isthe number of NSST candidates for each intra prediction mode. Themapping from an intra prediction mode to the transform set is defined ina table (1900) shown in FIG. 19. For example, a transform set applied toluma/chroma transform coefficients can be specified by the correspondingluma/chroma intra prediction modes according to the table (1900). Forintra prediction modes larger than 34 (e.g., diagonal predictiondirection), the transform coefficient block is transposed before/afterthe secondary transform at the encoder/decoder.

For each transform set, the selected non-separable secondary transformcandidate is further specified by an explicitly signaled CU-level NSSTindex. The index is signaled in a bitstream once per intra CU aftertransform coefficients and truncated unary binarization is used. Thetruncated value is 2 in case of planar or DC mode, and 3 for angularintra prediction mode. This NSST index is signaled only when there ismore than one non-zero coefficient in a CU. The default value is zerowhen it is not signaled. Zero value of this syntax element indicatessecondary transform is not applied to the current CU, values 1-3indicates which secondary transform from the set should be applied.

NSST may be not applied for a block coded with a transform skip mode.When an NSST index is signaled for a CU and not equal to zero, NSST isnot used for a block of a component that is coded with transform skipmode in the CU. When a CU with blocks of all components are coded intransform skip mode or the number of non-zero coefficients ofnon-transform-skip mode CBs is less than 2, the NSST index is notsignaled for the CU.

4.2 Reduced Size Transform (RST)

In some embodiments, a variant of NSST, referred to as reduced sizetransform (RST), or low-frequency non-separable secondary transform(LFNST), is employed. The RST uses a transform zero-out scheme. Whetherthe intra prediction mode is Planar or DC is checked for entropy codingthe transform index of NSST.

In an example, 4 transform sets are applied, and each transform setincludes three RST transform cores. The RST transform cores can have asize of 16×48 (or 16×64) (applied for transform coefficient block with aheight and width both being greater than or equal to 8) or 16×16(applied for transform coefficient block with either height or widthbeing equal to 4). For notational convenience, the 16×48 (or 16×64)transform is denoted as RST8×8 and the 16×16 one as RST4×4.

For RST8×8, two alternative transform coding processes (2000) and (2100)using 16×64 transform cores and 16×48 transform cores are shown in FIG.20 and FIG. 21, respectively. The one using 16×48 transform cores areadopted in VVC Draft 5.

In the process (2000) of the FIG. 20 example, at an encoder side, aforward primary transform (2010) can first be performed over a residualblock followed by a forward secondary transform (2012) over coefficientsgenerated from the forward primary transform (2010). In the forwardsecondary transform (2012), the 64 coefficients of the 4×4 sub-blocksA/B/C/D at the top-left corner of the coefficient block (2013) isrepresented into a 64-length vector, and multiplied with a transformmatrix of a size of 16×64 according to the equation (Eq. 3), resultingin a 16-length vector. The elements in the 16-length vector is filledback into the top-left 4×4 sub-block A of the coefficient block (2013).The coefficients in the sub-blocks B/C/D can take values of zero. Theresulting coefficients after the forward secondary transform 2012 arethen quantized at the step of (2014), and entropy-coded to generatecoded bits in a bitstream (2016).

The coded bits can be received at a decoder side, and entropy-decodedfollowed by a de-quantization (2024) to generate a coefficient block(2023). An inverse secondary transform (2022) can be performed over the16 coefficients at the top-left 4×4 sub-block E to obtain 64coefficients that are filled back to the 4×4 sub-blocks E/F/G/H.Thereafter, the coefficients in the block (2023) after the inversesecondary transform (2022) can be processed with an inverse primarytransform (2020) to obtain a recovered residual block.

The process (2100) of the FIG. 21 example is similar to the process(2000) except that fewer (48) coefficients are processed during theforward secondary transform (2012). Specifically, the 48 coefficients inthe sub-blocks A/B/C are processed with a smaller transform matrix of asize of 16×48. Usage of the smaller transform matrix can reduce a memorysize for storing the transform matrix, and respective computationcomplexity.

FIG. 22 shows an example CU-level syntax table (2200) where a syntaxelement lfnst_idx indicating a selection of a LFNST kernel is signaledat the end of CU-level syntax.

4.3 Examples of RST Computation

The main idea of a Reduced Transform (RT) is to map an N dimensionalvector to an R dimensional vector in a different space, where R/N (R<N)is the reduction factor.

The RST matrix is an R×N matrix as follows:

$\begin{matrix}{T_{R \times N} = \begin{bmatrix}t_{11} & t_{12} & t_{13} & \ldots & t_{1N} \\t_{21} & t_{22} & t_{23} & \ldots & r_{2N} \\\; & \vdots & \; & \ddots & \vdots \\t_{R1} & t_{R2} & t_{R3} & \ldots & t_{RN}\end{bmatrix}} & \left( {{Eq}.\mspace{11mu} 4} \right)\end{matrix}$

where the R rows of the transform are R bases of the N dimensionalspace. The inverse transform matrix for RT is the transpose of itsforward transform.

FIG. 23 shows a process (2301) of a reduced transform and a process(2302) of a reduced inverse transform. T represents an RST transformmatrix having a dimension of R×N, and T^(T) represents a transposematrix of T having a dimension of N×R.

In RST8×8, a reduction factor of 4 (¼ size) is realized. For example,instead of 64×64, which is a conventional 8×8 non-separable transformmatrix size, a 16×64 direct matrix is used. The 64×16 inverse RST matrixis used at the decoder side to generate core (primary) transformcoefficients in 8×8 top-left regions. The forward RST8×8 uses 16×64 (or8×64 for 8×8 block) matrices so that it produces non-zero coefficientsonly in the top-left 4×4 region within the given 8×8 region. In otherwords, if RST is applied then the 8×8 region except the top-left 4×4region will have only zero coefficients. For RST4×4, 16×16 (or 8×16 for4×4 block) direct matrix multiplication can be applied.

In addition, for RST8×8, to further reduce the transform matrix size,instead of the using the whole top-left 8×8 coefficients (shadedsub-blocks in FIG. 24A) of a residual block (2410) as input forcalculating a secondary transform, the top-left three 4×4 sub-blockcoefficients (shaded sub-blocks in FIG. 24B) of the residual block(2410) are used as the input for calculating the secondary transform.

In an example, an inverse RST is conditionally applied when thefollowing two conditions are satisfied: (i) a respective block size isgreater than or equal to the given threshold (W>=4 && H>=4), and (ii) atransform skip mode flag is equal to zero. For example, if both width(W) and height (H) of a transform coefficient block is greater than 4,then the RST8×8 is applied to the top-left 8×8 region of the transformcoefficient block. Otherwise, the RST4×4 is applied on the top-leftmin(8, W)×min(8, H) region of the transform coefficient block.

In an example, when an RST index is equal to 0, RST is not applied.Otherwise, RST is applied, and a kernel is chosen with the RST index. Inan example, RST is applied for intra CU in both intra and inter slices,and for both luma and chroma. If a dual tree is enabled, RST indices forluma and chroma are signaled separately. For inter slice (the dual treeis disabled), a single RST index is signaled and used for both luma andchroma. When an ISP mode is selected, RST is disabled, and RST index isnot signaled.

4.4 An Example of Selection of RST Transform Matrices

In an example, an RST matrix can be selected from four transform sets,each of which consists of two transforms. Which transform set is appliedcan be determined based on an applied intra prediction mode as follows.When one of three cross component linear model (CCLM) modes isindicated, transform set 0 can be selected. Otherwise, the transform setselection can be performed according to a table (2500) shown in FIG. 25.The index to access the table (2500), denoted by IntraPredMode, can bein a range of [−14, 83], which is a transformed mode index used for awide angle intra prediction for example.

5. Matrix-Based Intra Prediction (MIP) Mode

In some embodiments, a matrix-based intra prediction (MIP) mode isemployed. FIG. 26 shows an example process (2600) of the MIP mode. Forpredicting the samples of a rectangular block (2610) of width W andheight H, an MIP takes one line of H reconstructed neighboring boundarysamples at the left of the block (2610) and one line of W reconstructedneighboring boundary samples above the block (2610) as input. If thereconstructed samples are unavailable, the reconstructed samples can begenerated in a similar way as in a conventional intra prediction.

Generation of prediction signals can be based on the following threesteps from (2601) to (2603). At the step (2601), out of the boundarysamples, four samples in the case of W=H=4 and eight samples in allother cases are extracted by averaging.

At the step (2602), a matrix vector multiplication A_(k)·bdry_(red),followed by addition of an offset b_(k), is carried out with theaveraged samples bdry_(red) as an input. The result is a reducedprediction signal on a subsampled set of samples (2621) in the originalblock. The matrix A_(k) and the offset b_(k) can be selected based on anMIP mode index k.

At the step (2603), the prediction signal at the remaining positions(2622) is generated from the prediction signal on the subsampled set(2621) by a linear interpolation which is a single step linearinterpolation in each direction.

The matrices A_(k) and offset vectors b_(k) needed to generate theprediction signal can be taken from three sets S₀, S₁, S₂ of matrices.The set S₀ consists of 18 matrices A₀ ^(i), i ∈(0, . . . , 17) each ofwhich has 16 rows and 4 columns and 18 offset vectors b₀ ^(i), i∈(0, . .. , 17) each of size 16. Matrices and offset vectors of that set areused for blocks of size 4×4. The set S₁ consists of 10 matrices A₁ ^(i),i∈(0, . . . , 9), each of which has 16 rows and 8 columns and 10 offsetvectors b₁ ^(i), i∈(0, . . . , 9) each of size 16. Matrices and offsetvectors of that set are used for blocks of sizes 4×8, 8×4 and 8×8.Finally, the set S₂ consists of 6 matrices A₂ ^(i), i∈(0, . . . , 5),each of which has 64 rows and 8 columns and of 6 offset vectors b₂ ^(i),i∈(0, . . . , 5) of size 64. Matrices and offset vectors of that set orparts of these matrices and offset vectors are used for all otherblock-shapes.

As shown, given an 8×8 block (2610), MIP takes four averages along eachaxis of the boundary. The resulting eight input samples enter the matrixvector multiplication. The matrices are taken from the set S₁. Thisyields 16 samples (2621) on the odd positions of the prediction block.Thus, a total of (8·16)/(8·8)=2 multiplications per sample areperformed. After adding an offset, these samples are interpolatedvertically by using the reduced top boundary samples. Horizontalinterpolation follows by using the original left boundary samples. Theinterpolation process does not require any multiplications in this case.

5.1 Signaling of MIP Mode

In some embodiments, for each Coding Unit (CU) in intra mode, a flagindicating if an MIP mode is applied on the corresponding PredictionUnit (PU) or not can be sent in the bitstream. If an MIP mode isapplied, the index predmode of the MIP mode is signaled using anMPM-list including 3 MPMs.

The derivation of the MPMs can be performed using the intra-modes of theabove and the left PU as follows. There are three fixed mapping tablesmap_angular_to_mip_(idx), idx ∈{0,1,2}, and each table associate eachconventional intra prediction mode predmode_(Angular) with a specificMIP mode, as described in the following formula.

predmode_(MIP)=map_angular_to_mip[predmode_(Angular)]  (Eq. 5)

where map_angular_to_mip is a fixed look-up table. The index of themapping table is decided based on the width W and height H of PU, and intotal three indices are available, as described below,

idx(PU)=idx(W,H)∈{0,1,2}  (Eq. 6)

that indicates from which of the three sets the MIP parameters are to betaken above.

In some examples, to generate the MPM list for current block which iscoded by MIP mode, an above MIP mode, namely mode_(MIP) ^(above), and aleft MP mode, namely mode_(MIP) ^(left), are firstly derived.

The value of mode_(MIP) ^(above) can be derived as follows:

-   -   If the above PU PU_(above) is available, and it belongs to the        same CTU where the current PU resides, and PU_(above) is coded        by MIP using an MP mode

predmode_(MIP) ^(above) and idx(PU)=idx(PU _(above)),  (Eq. 7)

-   -   If the above PU PU_(above) is available, and it belongs to the        same CTU where the current PU resides, and PU_(above) is coded        using a conventional intra prediction mode predmode_(Angular)        ^(above),

mode_(MIP) ^(above)=map_angular_to_mip[predmode_(Angular)^(above)].  (Eq. 9)

-   -   Otherwise,

mode_(MIP) ^(above)=−1  (Eq. 10)

-   -   which means that this mode is unavailable.

The value of mode_(MIP) ^(left) is derived in the same way of derivingmode_(MIP) ^(above) but without checking whether the left PU belongs tothe same CTU where the current PU resides.

Finally, given the derived mode_(MIP) ^(above) and mode_(MIP) ^(left)and three pre-defined fixed default MPM lists list_(idx), idx∈{0,1,2}each of which contains three distinct MIP modes, an MPM list isconstructed. The MPM list is constructed based on the given default listlist_(idx(PU)) and mode_(MIP) ^(above) and mode_(MIP) ^(left), bysubstituting −1 by default values as well as removing duplicate MIPmodes.

As an example, FIG. 27 shows a CU-level syntax table where the flagssignaling MIP modes are shown in a frame (2701).

5.2 MPM-List Derivation for Conventional Intra-Prediction Modes

In some embodiments, the MIP modes are harmonized with the MPM-basedcoding of the conventional intra-prediction modes as follows. The lumaand chroma MPM-list derivation processes for the conventionalintra-prediction modes uses separate fixed tablesmap_mip_to_angular_(idx), idx∈{0,1,2}, which map an MIP-modepredmode_(MIP) to one of the conventional intra-prediction modes,

predmode_(Angular)=map_mip_to_angular[predmode_(MIP)].  (Eq. 11)

where map_mip_to_angular is a fixed look-up table. For the luma MPM-listderivation, whenever a neighboring luma block is coded by an MIP modepredmode_(MIP), this block is treated as if it was using theconventional intra-prediction mode predmode_(Angular). For the chromaMPM-list derivation, whenever the current luma block uses an MIP-mode,the same mapping is used to translate the MIP-mode to a conventionalintra prediction mode.

III. Implicit Transform Selection Enabling Based on High Level SyntaxElements or Block Level Syntax Elements

In some embodiments, two transform coding schemes, implicit transform(or referred to as implicit transform selection) and explicit transform(or referred to as explicit transform selection), can be employed.

In implicit transform, a group of non-DCT2 transforms (e.g., DST-1,DCT-5, DST-7, DCT-8, DST-4, DCT-4) can be selected without transformindex signaling. For example, a group of non-DCT2 transforms can beselected using already coded information that is available to both anencoder and a corresponding decoder. The already coded information caninclude, but not limited to, intra prediction mode (e.g., planar mode,DC mode, angular modes), block size, block width, block height, blockaspect ratio, block area size, intra coding mode (e.g., whether multiplereference line (MRL), ISP, MIP is used), position of selected spatialmerge candidates (e.g., top merge candidate, left merge candidate),inter prediction mode (e.g., inter position dependent predictioncombination (inter-PDPC) mode, combined inter intra prediction (CIIP)mode).

In contrast, in explicit transform, one transform can be selected from agroup of transform type candidates (such as DCT-2, DST-1, DCT-5, DST-7,DCT-8, DST-4, DCT-4) with an index signaled to indicate which transformtype is selected.

1. Implicit Transform Enabling when Explicit MTS is Disabled

In some embodiments, as described in the section II.3.2, for an intraprediction residual block which is not coded by ISP, implicit transformselection can be enabled when explicit MTS is disabled for both intraand inter prediction residual blocks as indicated by high level syntax(HLS) elements. For example, when SPS syntax elements,sps_explicit_mts_intra_enabled_flag andsps_explicit_mts_interenabled_flag, are both 0, a decoder can determineto enable the implicit transform selection for pictures or blocksassociated with the SPS syntax elements.

As an example, FIGS. 28A-28B in combination show a text (2800)specifying a transform coding process of performing explicit or implicittransform selection for a current block based on related syntax elementsreceived from a bitstream. The text (2800) can be used as a part of avideo coding standard. Two sections (2801) and (2802) are shown in FIG.28A, and one section (2803) and two tables (2804) and (2805) are shownin FIG. 28B.

In the section (2801), inputs to and output of the transform codingprocess are described. Specifically, location, size, color component,inverse-quantized transform coefficients of the current block are theinputs, and residual samples after an inverse transform processing usingselected transforms are the output.

In the section (2802), derivation of a variable, denoted byimplicitMtsEnabled, is described. The variable indicates whetherimplicit selection is enabled. As described, if an SPS syntax element,sps_mts_enabled_flag, is equal to 1 (which indicates MTS is enabled forpictures or blocks associated with this SPS syntax element),implicitMtsEnabled is equal to 1 when one of the three followingconditions is true: (i) an ISP is used for coding the current block;(ii) SBT is enabled and both sides of the current block is smaller orequal to 32, which indicates SBT is used; or (iii)sps_explicit_mts_intra_enabled_flag andsps_explicit_mts_inter_enabled_flag are both equal to 0 (which indicatesexplicit MTS is disabled for both intra and inter coded blocks), and thecurrent block is intra coded. Otherwise, implicitMtsEnabled is set equalto 0, which indicating implicit transform selection is disabled for thecurrent block.

As described in the section (2802), according to condition (i), for anintra predicted block coded with an ISP mode, implicit transform can beenabled for coding this intra predicted block. According to condition(iii), for an intra predicted block not coded with an ISP mode, whenexplicit MTS is disabled for both intra and inter predicted blocks,implicit transform can be enabled for coding the intra predicted blocknot coded with the ISP mode.

In the section (2803), vertical and horizontal transforms are determinedaccording to the variable implicitMtsEnabled, the inputs to the process,and the related syntax elements. For example, when bothsps_explicit_mts_intra_enabled_flag andsps_explicit_mts_inter_enabled_flag are equal to 0, the current block(that is of luma component and intra predicted) can be given ahorizontal transform kernel (indicated by trTypeHor) and a verticaltransform kernel (indicated by trTypeBer) according to expressions (3-1)and (3-2), respectively.

In the tables (2804) and (2805), the numbers 1 and 2 for indicatinghorizontal or vertical transform kernel types indicate a DST-7 transformand a DCT-8 transform, respectively, while the number 0 indicates aDCT-2 transform. In some examples, DST-4 transforms can be used in placeof the DST-7 transforms.

In the examples of FIGS. 28A-28B, for blocks controlled by the HLSelements sps_explicit_mts_intra_enabled_flag andsps_explicit_mts_inter_enabled_flag, explicit MTS for inter coded blocksand implicit transform for intra coded blocks (non-ISP coded) cannot becoexist. However, implicit transform selection on intra predictionresidual block does not need to be necessarily dependent on a HLSelement (e.g., sps_explicit_mts_inter_enabled_flag) controlling MTSenabling for inter prediction residuals. Thus, in some embodiments, foran intra-coded block which is not predicted by ISP mode, whetherimplicit transform can be applied depends on whether MTS can be appliedfor intra prediction residual (e.g., a value ofsps_explicit_mts_intra_enabled_flag), but does not depend on whether MTScan be applied for inter prediction residual (a value ofsps_explicit_mts_inter_enabled_flag). With such a control mechanism, itis allowed to have inter MTS (explicit MTS applied to an interpredication residual block) and implicit transform (for intra predictionresiduals) both enabled simultaneously.

For example, a first and second HLS elements can be received at adecoder. The first and second HLS elements control a same set ofpictures or regions (e.g., a vide sequence, a picture, a slice, a tile,and the like) that can include intra coded residual blocks and intercoded residual blocks. The first HLS element indicates whether explicitMTS is enabled or disabled for the respective intra coded residualblocks, while the second HLS element indicates whether explicit MTS isenabled or disabled for the respective inter coded residual blocks. Withrespect to the term of inter MTS, an explicit MTS applied to an intracoded residual block can be referred to as an intra MTS.

When the first HLS element indicates explicit MTS is disabled for theintra coded residual blocks, the decoder can accordingly determine toenable implicit transform (or implicit MTS) for the intra coded blockswithout considering a value of the second HLS element. For example, thesecond HLS element can be either 0 or 1, which does not affect theenabling of the implicit transform for the intra coded residual block.

As an example, FIG. 29 shows modifications (2900) to the text (2800)that correspond to the implicit transform enabling scheme where implicittransform for intra residual blocks and explicit transform for interresidual blocks can coexist. In the modifications (2900), a removed textis marked with a strikethrough, while an added text is marked with anunderline. As shown, the condition ofsps_explicit_mts_inter_enabled_flag being 0 has been removed.

2. Implicit Transform Disabling when Other Coding Tools are Enabled

In some embodiments, whether an implicit transform can be applied to anintra coded block (that is not predicted by ISP mode) depends on whethera specific coding tool is enabled as indicate by a HLS element.

2.1 when NSST is Enabled

In an embodiment, an implicit transform can be disabled for an intracoded block (that is not predicted by ISP mode) when a HLS elementindicates NSST is enabled. For example, as described in the sectionII.4.1, the transform matrix T is used in the equation (Eq. 3) for thesecondary transform processing. The transform matrix T can includeconstant elements, and be designed with an assumption of a certainstatistics of targeted coefficient blocks, such as coefficient blocksresulting from an explicit transform selection. Thus, a coefficientblock resulting from an implicit transform selection may not match withthe NSST in terms of statistics of respective coefficients. For example,applying an NSST to results of an implicit transform may not improvecoding performance. For the above reason, disabling implicit transformwhen NSST is enabled may be desirable.

In this disclosure, the term NSST can be used to refer to a family ofnon-separable secondary transform coding schemes, such as the initialdesign of NSST, RST, LFNST, or the like.

For example, a decoder may receive two HLS elements: one HLS element(e.g., sps_explicit_mts_intra_enabled_flag) indicates explicit MTS isdisabled, while the other HLS element (e.g., sps_lfnst_enabled_flag)indicates an NSST is enabled. Accordingly, the decoder can determine notto enable an implicit transform for intra coded blocks controlled bythose two HLS elements. In contrast, if one HLS element indicatesexplicit MTS is disabled, and the other HLS element indicates an NSST isalso disabled, the decoder can determine to enable an implicit transformfor respective intra coded blocks.

As an example, FIG. 30 shows modifications (3000) to the text (2800)that correspond to a scenario where an implicit transform is enabledwhen an NSST is disabled. As shown, an additional restriction,“sps_lfnst_enabled_flag is equal to 0”, is added to the condition (iii)for deriving the variable implicitNtsEnabled.

2.2 when MIP is Enabled

Similar to the scenario where an NSST is enabled, in some embodiments,implicit transform is disabled for an intra coded block (that is notpredicted by ISP mode) when a HLS element indicates an MIP is enabled.For example, applying an MIP intra coding mode to a block may resultingin a residual block having different statistics from residual blockscoded with regular intra modes. Thus, a residual block coded with MIPmay not match with implicit transform which may assume residualstatistics resulting from regular intra modes. Therefore, disablingimplicit transform may be desirable when an MIP is enabled.

For example, a decoder may receive two HLS elements: one HLS element(e.g., sps_explicit_mts_intra_enabled_flag) indicates explicit MTS isdisabled, while the other HLS element (e.g., sps_mip_enabled_flag)indicates an MIP is enabled. Accordingly, the decoder can determine notto enable an implicit transform for intra coded blocks controlled bythose two HLS elements. In contrast, if both the explicit MTS and theMIP are disabled as indicated by the two HLS elements, the decoder candetermine to enable an implicit transform for respective intra codedblocks.

As an example, FIG. 31 shows modifications (3100) to the text (2800)that correspond to a scenario where an implicit transform is enabledwhen an MIP is disabled. As shown, an additional restriction,“sps_mip_enabled_flag is equal to 0”, is added to the condition (iii)for deriving the variable implicitNtsEnabled.

3. Implicit Transform Enabling Based on Block Level Syntax Elementindications

In some embodiments, whether an implicit transform can be applied to anintra coded block (that is not predicted by ISP mode) depends on whetherMTS, NSST or MIP is applied to the intra coded block as indicate byblock level syntax elements.

3.1 when MTS and NSST are not Applied

In an embodiment, whether implicit transform can be applied to an intracoded block depends on whether both MTS and NSST are not applied to theintra coded block as indicated by block level syntax elements.

For example, a decoder can receive a first and second CU level (or blocklevel) syntax elements associated with a current block that is intracoded and not predicted by ISP mode. The current block may be located ata position of coordinates [x0] [y0] within a picture.

The first CU level syntax element (e.g., tu_mts_idx[x0] [y0]) mayindicate DCT-2 transforms can be used for the current block instead oftransforms used in MTS (e.g., DST-7, DCT-8, DCT-4, or the like). As anexample, in the table (2804), when tu_mts_idx[x0] [y0] has a value of 0,the variables of trTypeHor and trTypeVer both have a value of 0, whichindicates the horizontal and vertical transforms are DCT-2 transforms,and no DST-7 or DCT-8 transforms are applied. The second CU level syntaxelement (e.g., lfnst_idx [x0] [y0]) may indicate NSST is not applied tothe current block. Based on the above first and second CU level syntaxelements, the decoder can determine to enable an implicit MTS for thecurrent block.

In contrast, if the first and second CU level syntax elements indicateMTS is applied (tu_mts_idx[x0] [y0] has a value of 1, 2, 3, or 4), orNSST is applied (lfnst_idx [x0] [y0] has a non-zero value), the decodercan determine to disable an implicit MTS.

As an example, FIG. 32 shows modifications (3200) to the text (2800)that correspond to a scenario where both MTS and NSST are not applied toa current block. As shown, the original condition (iii) in the text(2800) is replaced with a condition that two CU level syntax elements“tu_mts_idx[x0][y0] and lfnst_idx[x0][y0] are both equal to 0”.

3.2 when MTS, NSST, and MIP are not Applied

In an embodiment, whether implicit transform can be applied to an intracoded block depends on whether MTS, NSST, and MIP are not applied to theintra coded block as indicated by block level syntax elements. Comparedwith the section III.3.1, one more coding tool, MIP, is additionallyconsidered.

For example, a decoder can receive a first, second, and third CU level(or block level) syntax elements associated with a current block that isintra coded and not predicted by ISP mode. The current block may belocated at a position of coordinates [x0] [y0] within a picture.

The first CU level syntax element (e.g., tu_mts_idx[x0] [y0]) mayindicate DCT-2 transforms can be used for the current block instead oftransforms used in MTS. The second CU level syntax element (e.g.,lfnst_idx [x0] [y0]) may indicate NSST is not applied to the currentblock. The third CU level syntax element (e.g., tu_mip_flag) mayindicate MIP is not applied to the current block. Based on the abovethree CU level syntax elements, the decoder can determine to enable animplicit MTS for the current block.

In contrast, if the above three CU level syntax elements indicate MTS isapplied (tu_mts_idx[x0] [y0] has a value of 1, 2, 3, or 4), NSST isapplied (lfnst_idx [x0] [y0] has a non-zero value), or MIP is applied(tu_mip_flag has a value of 1), the decoder can determine to disable animplicit MTS.

As an example, FIG. 33 shows modifications (3300) to the text (2800)that correspond to a scenario where none of MTS, NSST, or MIP is appliedto a current block. As shown, the original condition (iii) in the text(2800) is replaced with a condition that three CU level syntax elements“tu_mts_idx[x0][y0], intra_mip_flag[x0][y0] and lfnst_idx[x0][y0] areall equal to 0”.

4. Examples of Transform Coding Processes

FIGS. 34-36 show flow charts of transform coding processes (3400),(3500), and (3600) according to some embodiments of the disclosure. Theprocesses (3400), (3500), and (3600) can be used in inverse transformprocessing at a decoder to generate a residual block for a block underreconstruction. In various embodiments, the processes (3400), (3500),and (3600) can be executed by processing circuitry, such as theprocessing circuitry in the terminal devices (210), (220), (230) and(240), the processing circuitry that performs functions of the videodecoder (310), the processing circuitry that performs functions of thevideo decoder (410), and the like. In some embodiments, the processes(3400), (3500), and (3600) can be implemented in software instructions,thus when the processing circuitry executes the software instructions,the processing circuitry performs the processes (3400), (3500), and(3600).

4.1 the Process (3400): Implicit Transform Enabling when Explicit MTS isDisabled

The process (3400) starts from (S3401), and proceeds to (S3410).

At (S3410), a first HLS element is received at a decoder. The first HLSelement can indicate whether an explicit MTS is disabled for an intracoded block. For example, the intra coded block is under reconstruction,and thus can be referred to as a currant block. The first HLS elementmay be associated with a set of coding blocks that include the currentblock.

At (S3420), a second HLS element is received at the decoder. The secondHLS element can indicate whether an explicit MTS is enabled for an intercoded block. For example, the second HLS element can be associated withthe same set of coding blocks as the first HLS element. Both the currentblock and the inter coded block are included in the set of codingblocks.

At (S3430), the decoder can determine to enable implicit MTS for thecurrent block when the first HLS element indicates the explicit MTS isdisabled for the intra coded block, and the second HLS element indicatesthe explicit MTS is enabled for the inter coded block. The process(3400) can proceed to (S3499), and terminates at (S3499).

4.2 the Process (3500): Implicit Transform Disabling when Other CodingTools are Enabled

The process (3500) starts from (S3501), and proceeds to (S3510).

At (S3510), a first HLS element is received at a decoder. The first HLSelement can indicate whether an explicit MTS is enabled for an intracoded block. The intra coded block can be a block under reconstruction.The first HLS element controls a set of coding blocks including theintra coded block.

At (S3520), a second HLS element is received at the decoder. The secondHLS element can indicate whether an NSST or MIP is disabled for theintra coded block. For example, the second HLS element can control thesame set of coding blocks as the first HLS element.

At (S3530), the decoder can determine whether to enable an implicit MTSfor processing the intra coded block based on the first and second HLSelements. For example, the decoder can determine to enable the implicitMTS for the intra coded block when the first HLS element indicates theexplicit MTS is disabled for the intra coded block, and the second HLSelement indicates the NSST or the MIP is disabled for the intra codedblock. Alternatively, the decoder can determine to disable the implicitMTS for the intra coded block when the first HLS element indicates theexplicit MTS is disabled for the intra coded block, but the second HLSelement indicates the NSST or the MIP is enabled for the intra codedblock. The process (3500) can proceed to (S3599), and terminates at(S3599).

4.3 the Process (3600): Implicit Transform Enabling Based on Block LevelSyntax Element Indications

The process (3600) starts from (S3601), and proceeds to (S3610).

At S(3610), an intra coded block is received at a decoder. The intracoded block can be associated with a first block level syntax elementindicating whether an MTS is applied, and a second block level syntaxelement indicating whether an NSST is applied. For example, the intracoded block belongs to a CU that includes CU level syntax elementsincluding the first and second block level syntax elements.

At (S3620), the decoder can determine whether to enable an implicit MTSfor the intra coded block based on the first and second block levelsyntax elements. For example, the decoder can determine to enable theimplicit MTS for the intra coded block when the first block level syntaxelement indicates the MTS is not applied, and the second block levelsyntax element indicates the NSST is not applied. Alternatively, thedecoder can determine to disable the implicit MTS for the intra codedblock when the first block level syntax element indicates the MTS is notapplied, but the second block level syntax element indicates the NSST isapplied. The process (3600) can proceeds to (S3699), and terminates at(S3699).

IV. Computer System

The techniques described above, can be implemented as computer softwareusing computer-readable instructions and physically stored in one ormore computer-readable media. For example, FIG. 37 shows a computersystem (3700) suitable for implementing certain embodiments of thedisclosed subject matter.

The computer software can be coded using any suitable machine code orcomputer language, that may be subject to assembly, compilation,linking, or like mechanisms to create code comprising instructions thatcan be executed directly, or through interpretation, micro-codeexecution, and the like, by one or more computer central processingunits (CPUs), Graphics Processing Units (GPUs), and the like.

The instructions can be executed on various types of computers orcomponents thereof, including, for example, personal computers, tabletcomputers, servers, smartphones, gaming devices, internet of thingsdevices, and the like.

The components shown in FIG. 37 for computer system (3700) are exemplaryin nature and are not intended to suggest any limitation as to the scopeof use or functionality of the computer software implementingembodiments of the present disclosure. Neither should the configurationof components be interpreted as having any dependency or requirementrelating to any one or combination of components illustrated in theexemplary embodiment of a computer system (3700).

Computer system (3700) may include certain human interface inputdevices. Such a human interface input device may be responsive to inputby one or more human users through, for example, tactile input (such as:keystrokes, swipes, data glove movements), audio input (such as: voice,clapping), visual input (such as: gestures), olfactory input (notdepicted). The human interface devices can also be used to capturecertain media not necessarily directly related to conscious input by ahuman, such as audio (such as: speech, music, ambient sound), images(such as: scanned images, photographic images obtain from a still imagecamera), video (such as two-dimensional video, three-dimensional videoincluding stereoscopic video).

Input human interface devices may include one or more of (only one ofeach depicted): keyboard (3701), mouse (3702), trackpad (3703), touchscreen (3710), data-glove (not shown), joystick (3705), microphone(3706), scanner (3707), camera (3708).

Computer system (3700) may also include certain human interface outputdevices. Such human interface output devices may be stimulating thesenses of one or more human users through, for example, tactile output,sound, light, and smell/taste. Such human interface output devices mayinclude tactile output devices (for example tactile feedback by thetouch-screen (3710), data-glove (not shown), or joystick (3705), butthere can also be tactile feedback devices that do not serve as inputdevices), audio output devices (such as: speakers (3709), headphones(not depicted)), visual output devices (such as screens (3710) toinclude CRT screens, LCD screens, plasma screens, OLED screens, eachwith or without touch-screen input capability, each with or withouttactile feedback capability—some of which may be capable to output twodimensional visual output or more than three dimensional output throughmeans such as stereographic output; virtual-reality glasses (notdepicted), holographic displays and smoke tanks (not depicted)), andprinters (not depicted).

Computer system (3700) can also include human accessible storage devicesand their associated media such as optical media including CD/DVD ROM/RW(3720) with CD/DVD or the like media (3721), thumb-drive (3722),removable hard drive or solid state drive (3723), legacy magnetic mediasuch as tape and floppy disc (not depicted), specialized ROM/ASIC/PLDbased devices such as security dongles (not depicted), and the like.

Those skilled in the art should also understand that term “computerreadable media” as used in connection with the presently disclosedsubject matter does not encompass transmission media, carrier waves, orother transitory signals.

Computer system (3700) can also include an interface to one or morecommunication networks. Networks can for example be wireless, wireline,optical. Networks can further be local, wide-area, metropolitan,vehicular and industrial, real-time, delay-tolerant, and so on. Examplesof networks include local area networks such as Ethernet, wireless LANs,cellular networks to include GSM, 3G, 4G, 5G, LTE and the like, TVwireline or wireless wide area digital networks to include cable TV,satellite TV, and terrestrial broadcast TV, vehicular and industrial toinclude CANBus, and so forth. Certain networks commonly require externalnetwork interface adapters that attached to certain general purpose dataports or peripheral buses (3749) (such as, for example USB ports of thecomputer system (3700)); others are commonly integrated into the core ofthe computer system (3700) by attachment to a system bus as describedbelow (for example Ethernet interface into a PC computer system orcellular network interface into a smartphone computer system). Using anyof these networks, computer system (3700) can communicate with otherentities. Such communication can be uni-directional, receive only (forexample, broadcast TV), uni-directional send-only (for example CANbus tocertain CANbus devices), or bi-directional, for example to othercomputer systems using local or wide area digital networks. Certainprotocols and protocol stacks can be used on each of those networks andnetwork interfaces as described above.

Aforementioned human interface devices, human-accessible storagedevices, and network interfaces can be attached to a core (3740) of thecomputer system (3700).

The core (3740) can include one or more Central Processing Units (CPU)(3741), Graphics Processing Units (GPU) (3742), specialized programmableprocessing units in the form of Field Programmable Gate Areas (FPGA)(3743), hardware accelerators for certain tasks (3744), and so forth.These devices, along with Read-only memory (ROM) (3745), Random-accessmemory (3746), internal mass storage such as internal non-useraccessible hard drives, SSDs, and the like (3747), may be connectedthrough a system bus (3748). In some computer systems, the system bus(3748) can be accessible in the form of one or more physical plugs toenable extensions by additional CPUs, GPU, and the like. The peripheraldevices can be attached either directly to the core's system bus (3748),or through a peripheral bus (3749). Architectures for a peripheral businclude PCI, USB, and the like.

CPUs (3741), GPUs (3742), FPGAs (3743), and accelerators (3744) canexecute certain instructions that, in combination, can make up theaforementioned computer code. That computer code can be stored in ROM(3745) or RAM (3746). Transitional data can be also be stored in RAM(3746), whereas permanent data can be stored for example, in theinternal mass storage (3747). Fast storage and retrieve to any of thememory devices can be enabled through the use of cache memory, that canbe closely associated with one or more CPU (3741), GPU (3742), massstorage (3747), ROM (3745), RAM (3746), and the like.

The computer readable media can have computer code thereon forperforming various computer-implemented operations. The media andcomputer code can be those specially designed and constructed for thepurposes of the present disclosure, or they can be of the kind wellknown and available to those having skill in the computer software arts.

As an example and not by way of limitation, the computer system havingarchitecture (3700), and specifically the core (3740) can providefunctionality as a result of processor(s) (including CPUs, GPUs, FPGA,accelerators, and the like) executing software embodied in one or moretangible, computer-readable media. Such computer-readable media can bemedia associated with user-accessible mass storage as introduced above,as well as certain storage of the core (3740) that are of non-transitorynature, such as core-internal mass storage (3747) or ROM (3745). Thesoftware implementing various embodiments of the present disclosure canbe stored in such devices and executed by core (3740). Acomputer-readable medium can include one or more memory devices orchips, according to particular needs. The software can cause the core(3740) and specifically the processors therein (including CPU, GPU,FPGA, and the like) to execute particular processes or particular partsof particular processes described herein, including defining datastructures stored in RAM (3746) and modifying such data structuresaccording to the processes defined by the software. In addition or as analternative, the computer system can provide functionality as a resultof logic hardwired or otherwise embodied in a circuit (for example:accelerator (3744)), which can operate in place of or together withsoftware to execute particular processes or particular parts ofparticular processes described herein. Reference to software canencompass logic, and vice versa, where appropriate. Reference to acomputer-readable media can encompass a circuit (such as an integratedcircuit (IC)) storing software for execution, a circuit embodying logicfor execution, or both, where appropriate. The present disclosureencompasses any suitable combination of hardware and software.

APPENDIX A: ACRONYMS

-   AMT: Adaptive Multiple Transform-   ASIC: Application-Specific Integrated Circuit-   BMS: benchmark set-   CANBus: Controller Area Network Bus-   CCLM: Cross-Component Linear Model-   CD: Compact Disc-   COT: Compound Orthonormal Transform-   CPUs: Central Processing Units-   CRT: Cathode Ray Tube-   CTBs: Coding Tree Blocks-   CTUs: Coding Tree Units-   CU: Coding Unit-   DVD: Digital Video Disc-   EMT: Enhanced Multiple Transform-   FPGA: Field Programmable Gate Areas-   GOPs: Groups of Pictures-   GPUs: Graphics Processing Units-   GSM: Global System for Mobile communications-   HDR: high dynamic range-   HEVC: High Efficiency Video Coding-   HLS: High-Level Syntax-   HRD: Hypothetical Reference Decoder-   IBC: Intra Block Copy-   IC: Integrated Circuit-   MT: Identity transform-   ISP: Intra Sub-Partitioning-   JEM: joint exploration model-   JVET: Joint Video Exploration Team-   KLT: Karhunen-Loève Transform-   LAN: Local Area Network-   LCD: Liquid-Crystal Display-   LFNST: Low-Frequency Non-Separable Secondary Transform-   LTE: Long-Term Evolution-   MIP: Matrix-based Intra Prediction Mode-   MRL (or MRLP): Multiple reference line prediction-   MTS: Multiple Transform Selection-   MV: Motion Vector-   NSST: Non-Separable Secondary Transform-   OLED: Organic Light-Emitting Diode-   PBs: Prediction Blocks-   PCI: Peripheral Component Interconnect-   PLD: Programmable Logic Device-   PPS: Picture Parameter Set-   PU: Prediction Unit-   RAM: Random Access Memory-   ROM: Read-Only Memory-   RST: Reduced-Size Transform-   SBT: Sub-block Transform-   SDR: standard dynamic range-   SEI: Supplementary Enhancement Information-   SNR: Signal Noise Ratio-   SPS: Sequence Parameter Set-   SSD: solid-state drive-   SVT: Spatially Varying Transform-   TSM: Transform Skip Mode-   TUs: Transform Units,-   USB: Universal Serial Bus-   VPS: Video Parameter Set-   VUI: Video Usability Information-   VVC: versatile video coding

While this disclosure has described several exemplary embodiments, thereare alterations, permutations, and various substitute equivalents, whichfall within the scope of the disclosure. It will thus be appreciatedthat those skilled in the art will be able to devise numerous systemsand methods which, although not explicitly shown or described herein,embody the principles of the disclosure and are thus within the spiritand scope thereof.

What is claimed is:
 1. A method for video processing, comprising:receiving a first high level syntax (HLS) element indicating whether anexplicit multiple transform selection (MTS) is enabled or disabled for afirst block that is an intra coded block, wherein transform typeinformation indicating a transform type is signaled in the explicit MTS;receiving a second HLS element indicating whether the explicit MTS isenabled or disabled for a second block that is an inter coded block; andenabling an implicit MTS for the first block based on the first HLSelement indicating the explicit MTS is disabled for the first block andirrespective of whether the second HLS element indicates the explicitMTS is enabled or disabled for the second block, wherein the transformtype information is not signaled in the implicit MTS.
 2. The method ofclaim 1, further comprising: applying the implicit MTS to the intracoded block, wherein a transform type for processing the intra codedblock is determined according to a size of the intra coded block.
 3. Themethod of claim 1, wherein the first or second HLS element is one of: avideo parameter set (VPS) syntax element, a sequence parameter set (SPS)syntax element, a picture parameter set (PPS) syntax element, a sliceheader syntax element, a tile header syntax element, or a tile groupheader syntax element.
 4. The method of claim 1, wherein the intra codedblock is not coded with an intra sub-partitioning (ISP) mode.
 5. Themethod of claim 1, further comprising: receiving a third HLS elementindicating an MTS is enabled for each of the inter and intra codedblocks.
 6. The method of claim 1, wherein the transform type informationincludes an MTS index, the MTS index signaling the transform type forthe explicit MTS.
 7. The method of claim 1, wherein the enablingcomprises: determining whether to enable the implicit MTS for the intracoded block based on whether a non-separable secondary transform (NSST)and a matrix-based intra prediction (MIP) are applied to the intra codedblock.
 8. An apparatus for video processing, comprising circuitryconfigured to: receive a first high level syntax (HLS) elementindicating whether an explicit multiple transform selection (MTS) isenabled or disabled for a first block that is an intra coded block,wherein transform type information indicating a transform type issignaled in the explicit MTS; receive a second HLS element indicatingwhether the explicit MTS is enabled or disabled for a second block thatis an inter coded block; and enable an implicit MTS for the first blockbased on the first HLS element indicating the explicit MTS is disabledfor the first block and irrespective of whether the second HLS elementindicates the explicit MTS is enabled or disabled for the second block,wherein the transform type information is not signaled in the implicitMTS.
 9. The apparatus of claim 8, wherein the circuitry is furtherconfigured to: apply the implicit MTS to the intra coded block, whereina transform type for processing the intra coded block is determinedaccording to a size of the intra coded block.
 10. The apparatus of claim8, wherein the first or second HLS element is one of: a video parameterset (VPS) syntax element, a sequence parameter set (SPS) syntax element,a picture parameter set (PPS) syntax element, a slice header syntaxelement, a tile header syntax element, or a tile group header syntaxelement.
 11. The apparatus of claim 8, wherein the intra coded block isnot coded with an intra sub-partitioning (ISP) mode.
 12. The apparatusof claim 8, wherein the circuitry is further configured to: receive athird HLS element indicating an MTS is enabled for each of the inter andintra coded blocks.
 13. The apparatus of claim 8, wherein the transformtype information includes an MTS index, the MTS index signaling thetransform type for the explicit MTS.
 14. The apparatus of claim 8,wherein the circuitry is further configured to: determine whether toenable the implicit MTS for the intra coded block based on whether anon-separable secondary transform (NSST) and a matrix-based intraprediction (MIP) are applied to the intra coded block.
 15. Anon-transitory computer-readable medium storing instructions that, whenexecuted by a processor, cause the processor to perform a method forvideo processing, the method comprising: receiving a first high levelsyntax (HLS) element indicating whether an explicit multiple transformselection (MTS) is enabled or disabled for a first block that is anintra coded block, wherein transform type information indicating atransform type is signaled in the explicit MTS; receiving a second HLSelement indicating whether the explicit MTS is enabled or disabled for asecond block that is an inter coded block; and enabling an implicit MTSfor the first block based on the first HLS element indicating theexplicit MTS is disabled for the first block and irrespective of whetherthe second HLS element indicates the explicit MTS is enabled or disabledfor the second block, wherein the transform type information is notsignaled in the implicit MTS.
 16. The non-transitory computer-readablemedium of claim 15, wherein the method further comprises: applying theimplicit MTS to the intra coded block, wherein a transform type forprocessing the intra coded block is determined according to a size ofthe intra coded block.
 17. The non-transitory computer-readable mediumof claim 15, wherein the first or second HLS element is one of: a videoparameter set (VPS) syntax element, a sequence parameter set (SPS)syntax element, a picture parameter set (PPS) syntax element, a sliceheader syntax element, a tile header syntax element, or a tile groupheader syntax element.
 18. The non-transitory computer-readable mediumof claim 15, wherein the intra coded block is not coded with an intrasub-partitioning (ISP) mode.
 19. The non-transitory computer-readablemedium of claim 15, wherein the transform type information includes anMTS index, the MTS index signaling the transform type for the explicitMTS.
 20. The non-transitory computer-readable medium of claim 15,wherein the enabling comprises: determining whether to enable theimplicit MTS for the intra coded block based on whether a non-separablesecondary transform (NSST) and a matrix-based intra prediction (MIP) areapplied to the intra coded block.